Redundant Communications

Abstract

This paper presents the mapping of the redundancy protocols PRP, HSR in combination with IEEE 1588 clock synchronization onto a configurable CPU/FPGA based RedBox architecture. Whereas core functions of PRP, HSR and IEEE 1588 are mapped onto the FPGA, a CPU executes the control parts of these protocols. A standard switch ASIC provides direct connection to several network devices. Minimum size frames are forwarded by the FPGA at up to twice the speed of other implementations. Connected PRP/HSR RedBoxes and an IEEE 1588 clock master synchronize to within 30 ns. The RedBox can be integrated into time-synchronized industrial networks in order to improve the communications reliability.